module podreg
	(clock, resetn, load, DATA, Q);
input			clock, resetn;
input			load;
input	[15:0]	DATA;
output	[15:0]	Q;

reg		[15:0]	Q;

always @(posedge clock or negedge resetn)
begin
	if (!resetn) Q <= 16'b0;
	else if (load) Q <= DATA;
end
endmodule